As the use of digital data becomes wide spread, the electronic devices that use digital data, such as wireless communication devices, require larger and more effective memory systems to store and access the digital data. In addition, the number of these memory systems is increasing in system on chip designs along with increases in the clock frequency driving these memory systems. By increasing the clock frequency, memory systems are becoming a bottleneck for Power, Performance, and Area (PPA) of the chip. For such memory systems, clock latency is beneficial to meet the Setup Time on the inputs of the memory. However, clock latency has a negative impact on timing on the memory output paths. Improved timing at memory inputs and outputs can be translated into reduced power, improved system performance, or reduced system area. In other words, clock latency can improve PPA on the input side of memory, while it decreases PPA on the output side. Therefore, desired clocking system for memory system can be defined as (1) when writing to memory, higher clock latency is desirable and (2) when reading from memory, lower clock latency is desirable. However, current circuit design as well as place and route methods can only provide a constant clock latency, independent of read or write operation. This leads to a sub-optimal design depending on timing criticality on the input or output side. In other words, current designs only achieve one of the above situations for the clock latency.
Accordingly, there is a need for systems, apparatus, and methods that overcome the deficiencies of conventional approaches including the methods, system and apparatus provided hereby.